面向串扰时延效应的时序分析方法及在集成电路测试中的应用

随着特征尺寸进入纳米尺度,相邻连线之间的电容耦合对电路时序的影响越来越大,并可能使得电路在运行时失效.准确和快速地估计电路中的串扰效应影响,找到电路中潜在的串扰时延故障目标,并针对这些故障进行测试是非常必要的.文中提出了一种基于通路的考虑多串扰引起的时延效应的静态时序分析方法,该方法通过同时考虑临界通路及为其所有相关侵略线传播信号的子通路来分析多串扰耦合效应.该方法引入了新的数据结构"跳变图"来记录所有可能的信号跳变时间,能够精确地找到潜在的串扰噪声源,并在考虑串扰时延的情况下有效找到临界通路及引起其最大串扰减速效应的侵略子通路集.这种方法可以通过控制跳变图中时间槽的大小来平衡计算精度和运行时间.最后,文中介绍了在基于精确源串扰通路时延故障模型的测试技术中,该静态时序分析方法在耦合线对选择和故障敏化中的应用.针对ISCAS89电路的实验结果显示,文中提出的技术能够适应于大电路的串扰效应分析和测试,并且具有可接受的运行时间.

Crosstalk-Induced Delay Oriented Static Timing Analysis and Its Application to VLSI Test

As the feature size continues to shrink into the nanometer era,the crosstalk-induced effect on circuit timing becomes significant.It is essential that potential crosstalk-induced delay effects should be estimated,identified,tested accurately and quickly.This paper proposes a novel path-based static timing analysis technique for multiple coupling effects.In this method,multiple crosstalk-induced effects are analyzed by considering a critical path and the sub-paths which propagate the transition signals to the aggressor lines coupled to the critical path.A new structure,transition map,is introduced to record all the possible arrival time of a line.Based on it,we can accurately identify the potential crosstalk noise sources,and efficiently find critical paths in presence of crosstalk as well as proper sub-paths to activate maximal coupling effects on a critical path.We can trade off accuracy and runtime by controlling the size of time scale used in transition map,which makes this approach highly scalable.The application of this method to the delay test based on Precise Crosstalk-induced Path Delay Fault model is given.Experiments on ISCAS89 benchmark circuit show the proposed technique can be applied to analysis and test of crosstalk-induced effects for large circuits within an acceptable time.