VLSI晶体管级时延模拟方法

提出了一种新的晶体管级时延模拟方法，为了保证模拟的精度，综合考虑了存在于短沟道晶体管中的短路电流、输入／输出耦合电容和载流子速度饱和等效应对MOSFET晶体管沟道电流的影响，针对经典的ALPHA沟道电流分析模型（Alpha-Power-Law）进行了改良，以达到精确计算沟道电流的目的．该方法通过改良的节点分析方程（MNA）计算逻辑门的输出波形，以获得逻辑门的时间延迟和跳变时间．所开发的晶体管级时延模拟器性能优越，当逻辑门中某一晶体管的一个参数（如沟道长度、宽度或阈值电压％0）改变后，模拟器可以快速地计算出新的逻辑门输出波形．基于BSIM370nm工艺模型，采用HSPICE软件的模拟结果来验证该方法的效率与精确性．实验结果表明：该方法模拟效率高，模拟一个逻辑门平均仅需1．0ms；模拟精度高，在所有测试电路时延模拟结果中，最大误差仅为5．04％，平均误差为2．68％．

Transistor-Level Delay Simulation Methodology for VLSI Analysis

A novel transistor-level delay simulation method for nanometer technologies is proposed. It takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects of nanometer technology. The traditional Alpha-Power-Law MOSFET model is modified to accurately compute the channel current for today's transistor analysis, and the modified nodal analysis (MNA) equation is used to compute output waveforms for gate delay and transition time. When a transistor in a gate is subject to one parameter change such as channel width, length, or threshold voltage V_ T0 , our simulation method can fast compute output waveform of the gate. HSPICE of BSIM3 70nm technology is used to verify the accuracy of our simulation method. Experimental results show that our method only takes 1.0ms per gate with only 5.04%(maximum) and 2.68%(average) accuracy loss on delay.