SoC测试集成的研究环境构建

构建了一个具有结构和功能信息的研究环境,供与SoC测试集成相关的研究使用.该环境是一个包含典型功能模块和可测性设计（design for test,DFT）方法的SoC电路,其结构化的特点使它能应用于测试接口的设计与优化、测试访问机制的设计与优化、测试调度、基于P1500标准的测试集成方案设计等众多研究领域.

The Construction of a Research Environment for SoC Test Integration

A research environment is presented in this paper, which intends to be used in the research with regard to test integration. This environment is a system-on-a-chip which is composed of typical functional blocks and DFT schemes. It will be shipped to users in the form of gate-list, which enables it to disclose the details that one test integration scheme may encounter, verify the function completeness and provide realistic data for performance evaluation. Its structural nature makes it suitable for many research areas, such as test interface design and optimization, TAM design and optimization, test scheduling, P1500-compliant test integration scheme, etc.