| 通用CPU设计验证中的等价性检验方法 |
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| 引用本文： | 李光辉,邵明,李晓维. 通用CPU设计验证中的等价性检验方法[J]. 计算机辅助设计与图形学学报, 2005, 17(2): 230-235 |
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| 作者姓名： | 李光辉 邵明 李晓维 |
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| 作者单位： | 浙江林学院信息工程学院,杭州,311300;中国科学院计算技术研究所信息网络研究室,北京,100080;中国科学院研究生院,北京,100039;中国科学院计算技术研究所信息网络研究室,北京,100080;中国科学院研究生院,北京,100039 |
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| 基金项目： | 国家“八六三”高技术研究发展计划(2001AA111100)，国家自然科学基金重点项目(90207002)，北京市重点科技项目(H020120120130)，浙江省自然科学基金(M603097) |
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| 摘 要： | 针对传统的模拟验证方法需要大量的时间且难以获得完全的覆盖率的局限性，提出了目前应用最广泛的一种形式验证方法——等价性检验在一款通用CPU设计验证中的应用方案，包括寄存器传输级(RTL)设计与门级网表、门级网表与门级网表、RTL设计与RTL设计之间的功能等价性验证．此外，给出了验证过程中一些常见问题的解决办法．验证结果表明了该方法的可行性，显著地减少了门级模拟的时间．
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| 关 键 词： | 形式验证 模拟 等价性检验 比较点匹配 |
Equivalence Checking for General Purpose CPU Design Verification |
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| Li Guanghui,Shao Ming,Li Xiaowei. Equivalence Checking for General Purpose CPU Design Verification[J]. Journal of Computer-Aided Design & Computer Graphics, 2005, 17(2): 230-235 |
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| Authors: | Li Guanghui Shao Ming Li Xiaowei |
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| Affiliation: | Li Guanghui 1,2,3) Shao Ming 2,3) Li Xiaowei 2,3) 1) |
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| Abstract: | With the increasing complexity of integrated circuits designs, functional verification has become the bottle-neck of design flow. The traditional simulation based validation is very time-consuming and incomplete. An alternative technique is formal verification, it needs no test vector, and can reduce the design cycle with full functional coverage. In this paper, we present an equivalence checking scheme for verifying a general purpose CPU design, including proving the equivalence of two designs in different levels of abstraction (e.g. RTL to gates, gates to gates, RTL to RTL). The techniques to solve some common problems are proposed. The verification results show that the proposed scheme can reduce the gate-level simulation time significantly, and increase confidence in the system design. |
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| Keywords: | formal verification simulation equivalence checking compare point matching |
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