首页 | 本学科首页   官方微博 | 高级检索  
     

减少多种子内建自测试方法硬件开销的有效途径
引用本文:李立健,赵瑞莲.减少多种子内建自测试方法硬件开销的有效途径[J].计算机辅助设计与图形学学报,2003,15(6):662-666,672.
作者姓名:李立健  赵瑞莲
作者单位:1. 中国科学院自动化研究所国家专用集成电路工程中心,北京,100080
2. 北京化工大学计算机科学与技术系,北京,100029
基金项目:国家自然科学基金 ( 60 173 0 42 )资助
摘    要:提出一个基于重复播种的新颖的BIST方案,该方案使用侦测随机向量难测故障的测试向量作为种子,并利用种子产生过程中剩余的随意位进行存储压缩;通过最小化种子的测试序列以减少测试施加时间.实验表明,该方案需要外加硬件少,测试施加时间较短,故障覆盖率高,近似等于所依赖的ATPG工具的故障覆盖率.在扼要回顾常见的确定性BIST方案的基础上,着重介绍了文中的压缩存储硬件的方法、合成方法和实验结果.

关 键 词:存储压缩  故障覆盖率  寄存器  集成电路  电路测试  多种子内建自测试

Effective Measures to Reduce Hardware Overhead on Multiseeding BIST
Li Lijian,Zhao Ruilian.Effective Measures to Reduce Hardware Overhead on Multiseeding BIST[J].Journal of Computer-Aided Design & Computer Graphics,2003,15(6):662-666,672.
Authors:Li Lijian  Zhao Ruilian
Affiliation:Li Lijian 1) Zhao Ruilian 2) 1)
Abstract:This paper presents a novel build in self test (BIST) approach by reseeding an LFSR It adopts test patterns used to detect random pattern resistant faults as its seeds Don't care bits in those seeds, which are remained during the process of test pattern generation by an automatic test pattern generator (ATPG) tool, are utilized to reduce the size of storage of a seed array Experimental results show that the proposed approach is able to achieve higher fault coverage, which is approximately equal to the one of an ATPG on which the approach depends, and needs less additional hardware overhead for synthesis, and consumes less time for test pattern application After a brief review of those typical deterministic BIST schemes, this paper mainly introduces its scheme of storage compression, synthesis methodology, and experimental results
Keywords:linear  feedback shift  register  seed  random pattern resistant fault  don't care bit
本文献已被 CNKI 维普 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号