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| 嵌入式处理器在片调试功能的设计与实现 | |
| 引用本文： | 黄海林,范东睿,许彤,朱鹏飞,郑保建,曹非,陈亮.嵌入式处理器在片调试功能的设计与实现[J].计算机辅助设计与图形学学报,2006,18(7):1005-1010. |
| 作者姓名： | 黄海林 范东睿 许彤 朱鹏飞 郑保建 曹非 陈亮 |
| 作者单位： | 1. 中国科学院计算技术研究所系统结构研究室,北京,100080;中国科学院研究生院,北京,100039 2. 中国科学院计算技术研究所系统结构研究室,北京,100080 3. 北京神州龙芯集成电路设计有限公司,北京,100083 |
| 基金项目： | 中国科学院知识创新工程项目;国家高技术研究发展计划(863计划);国家科技攻关项目 |
| 摘 要： | 以龙芯1号处理器为研究对象,探讨了嵌入式处理器中在片调试功能的设计实现方法.通过扩充IEEEP1149.1协议的JTAG测试访问端口（TAP）,并在处理器内部增加控制模块,实现了软件调试断点、调试中断、硬件断点以及单步执行等多种在片调试功能.调试主机只需要通过一根JTAG调试电缆就可以访问目标处理器内部寄存器等各种资源,并控制目标处理器的运行过程,实现了处理器的在片调试功能,大大地方便了软件开发与系统调试. |
| 关 键 词： | 在片调试 龙芯1号处理器 |
| 收稿时间： | 2005-06-08 |
| 修稿时间： | 2005-09-05 |
Design and Implementation of On-chip Debug Features in Embedded Processor |
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| Huang Hailin,Fan Dongrui,Xu Tong,Zhu Pengfei,Zheng Baojian,Cao Fei,Chen Liang.Design and Implementation of On-chip Debug Features in Embedded Processor[J].Journal of Computer-Aided Design & Computer Graphics,2006,18(7):1005-1010. | |
| Authors: | Huang Hailin Fan Dongrui Xu Tong Zhu Pengfei Zheng Baojian Cao Fei Chen Liang |
| Affiliation: | 1. Computer Architecture Laboratory, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080; 2. Graduate University of Chinese Academy of Sciences, Beijing 100039; 3. BLX IC Design Co. ,Ltd, Beijing 100080 |
| Abstract: | With Godson-1 processor as the research prototype,a design scheme of on-chip debug features in embedded processor is presented in this paper.In the scheme the IEEE P1149.1 JTAG TAP module is extended and some control logic is added inside the processor core to provide the following new capabilities for software and system debug: software debug breakpoint,debug interrupt,hardware breakpoint, single-step execution,etc.With only a JTAG debug cable,the debug host can access the internal resources and control the program running of the processor under debug.With these on-chip debug features,the software development and system debug are facilitated greatly. |
| Keywords: | IEEE P1149 1 JTAG |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |