| FSM状态间逻辑条件检验的算法研究 |
| |
| 引用本文： | 董云耀,何一兵.FSM状态间逻辑条件检验的算法研究[J].计算机辅助设计与图形学学报,1993,5(3):172-178. |
| |
| 作者姓名： | 董云耀 何一兵 |
| |
| 作者单位： | 杭州电子工业学院CAD研究所，杭州电子工业学院CAD研究所 杭州，310037，杭州，310037 |
| |
| 摘 要： | 有限状态机(FSM)是VLSI控制结构的一种映射,它的自动综合成为设计自动化的一个十分重要的环节和途径。本文讨论在FSM自动综合中输入阶段的状态间逻辑条件检验的问题,研究分析状态间逻辑条件检验的相互关系及影响,并提出了FSM状态间逻辑条件检验的优化算法,从而使时间复杂度降低,实现更加简便。最后,本文给出了优化算法的流程和一些实验结果,结果令人满意。
|
| 关 键 词： | 有限状态机 算法 设计 集成电路 |
A STUDY OF ALGORITHMS FOR VALIDATING LOGIC CONDITIONS AMONG FSM STATES |
| |
| Dong Yunyao He Yibing CAD center,Hangzhou Institute of Electronic Engineering,Hangzhou..A STUDY OF ALGORITHMS FOR VALIDATING LOGIC CONDITIONS AMONG FSM STATES[J].Journal of Computer-Aided Design & Computer Graphics,1993,5(3):172-178. |
| |
| Authors: | Dong Yunyao He Yibing CAD center Hangzhou Institute of Electronic Engineering Hangzhou |
| |
| Affiliation: | Dong Yunyao He Yibing CAD center,Hangzhou Institute of Electronic Engineering,Hangzhou. 310037 |
| |
| Abstract: | Finite state machine (FSM) is a reflection of VLSI control path, and its automatic synthesis becomes a very important step of design automation (DA). In this paper, we will discuss the problem of validating logic conditions among FSM states in the input phase of FSM automatic synthesis process, analyse the interaction between validations of logic conditions among FSM states, and propose a optimal algorithm for validating logic conditions among FSM states that will decrease the time complexity and be easy to implement. Finally, the flowchart of our optimal algorithm and some experimental results are also presented in this paper. |
| |
| Keywords: | Finite state machine logic synthesis design automation |
| 本文献已被 CNKI 维普 等数据库收录！ |
|
