考虑时延偏差的数字电路时延测试综述

先进集成电路工艺下，时延测试是数字电路测试的一项重要内容。各种时延偏差来源如小时延缺陷、工艺偏差、 串扰、电源噪声、老化效应等，影响着电路的额定时钟频率，是时延测试中需要考虑的因素。文章在介绍电路时延偏差 问题的各种来源的基础上，给出了针对不同的时延偏差问题所涉及的分析、建模、测试生成与电路设计等关键技术。进 一步介绍了中国科学院计算技术研究所近年来在考虑时延偏差的数字电路时延测试方面所做的研究工作，包括：考虑串 扰/电源噪声的时延测试、基于统计定时分析的测试通路选择、片上时延测量、超速测试、测试优化、在线时序检测等方 面。文章最后对数字电路时延测试技术的发展趋势进行了总结。

Review on Delay Testing of Digital Circuits Considering Delay Variations

Delay testing is very important for digital circuit testing in modern technologies of integrated circuits. Various sources of delay variations such as small delay defects, process variations, crosstalk, power supply noise and aging effects, affect the rated clock frequency of a design, and should be considered in delay testing. The cause of delay variations was introduced, and the related techniques on analysis, modeling, test generation, and circuit design according to different sources of delay variations were discussed. Furthermore, the main research results on delay testing of digital circuits considering delay variations in the Institute of Computing Technology, Chinese Academy of Sciences were introduced. The proposed techniques include delay testing considering crosstalk or power supply noise induced effects, statistical timing analysis based test path selection, super-speed testing, test optimization, and on-line timing checking, etc. Finally the trend of delay testing techniques for digital circuits was summarized.