改进的指令总线功耗优化策略

针对编译器系统设计和编译中的低功耗优化,基于可重定向编译器,实现在编译器后端对VLIW指令总线进行功耗优化的策略.通过对编译生成的二进制目标码进行横向再调度来减少指令总线上的高低电位切换次数,达到降低系统功耗的目的.对编译后端的软件流水和超块调度两种性能优化策略进行对比实验,表明其优化效果在30%以上,并且代码的指令级并行性(Instruction Level Parallelism,ILP)与优化效果存在明显的相关性.最后,通过ILP对该策略提出改进,以指令级并行信息指导功耗优化,在功耗优化效果损失不大的前提下,可节省多达20%的算法开销.

Improved low-power optimization strategy for stargeting instruction bus

With the design of complier system and optimization for its low-power in compiling, the low-power optimization strategy for VLIW instruction bus is implemented in the compiler backend. The strategy reduces the number of voltage switch on instruction bus by rescheduling the generated binary code in horizon, which leads to system power reduction. The comparison experiments for software pipeline and super block scheduling are done, which shows that the optimization effect can be increased by more than 30% and has obvious relation to instruction level parallelism (ILP). At last, an enhancement method for the strategy is proposed based on ILP information. The statistics shows that the cost saved can reach up to 20%.