| 基于FPGA的动态目标跟踪系统设计 |
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| 引用本文： | 吴长江,赵不贿,郑博,于小燕.基于FPGA的动态目标跟踪系统设计[J].电子技术应用,2010,36(3). |
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| 作者姓名： | 吴长江 赵不贿 郑博 于小燕 |
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| 作者单位： | 江苏大学电气信息工程学院,江苏,镇江,212013 |
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| 摘 要： | 为了解决基于PC机的视频动态目标跟踪实时性瓶颈问题,设计出一种基于FPGA的动态目标跟踪系统。设计遵循图像处理金字塔模型,针对低层和中层算法简单、数据量大且存在一定并行性等特点采用FPGA硬件实现,而高层较复杂算法使用Nios Ⅱ软核进行C语言编程。整个设计采用Verilog-HDL对算法完成建模与实现,并在QUARTUS Ⅱ上进行了综合、布线等工作,最后以Altera公司的DE2开发板为硬件平台实现了整个系统。
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| 关 键 词： | FPGA 视觉跟踪 Verilog-HDL 动态目标 NiosⅡ |
Moving target tracking system design based on FPGA |
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| WU Chang Jiang,ZHAO Bu Hui,ZHENG Bo,YU Xiao Yan.Moving target tracking system design based on FPGA[J].Application of Electronic Technique,2010,36(3). |
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| Authors: | WU Chang Jiang ZHAO Bu Hui ZHENG Bo YU Xiao Yan |
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| Affiliation: | WU Chang Jiang,ZHAO Bu Hui,ZHENG Bo,YU Xiao Yan (School of Electrical and Information Engineering,Jiangsu University,Zhenjiang 212013,China) |
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| Abstract: | In order to overcome the bottleneck of real-time in moving target tracking system based on PC, this paper designs a moving target tracking system based on FPGA. This design uses the pyramid model of image processing. As low and middle-lev-el algorithms are simple, the amounts of data are large and partially parallel, FPGA hardware implementation is adopted. Then more complex high-level algorithms use Nios II soft-core for C language programming to be resolved. The modeling and realization are achieved by Verilog-HDL , and synthesis and place&route are completed in Quartus Ⅱ software platform. Finally, this design im-plements on Ahera'DE2 development and education board hardware platform. |
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| Keywords: | FPGA Verilog-HDL Nios FPGA visual tracking Verilog-HDL moving target |
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