| 数字基带预失真系统中环路延迟估计的FPGA实现 |
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| 引用本文： | 刘正平,夏威,何子述.数字基带预失真系统中环路延迟估计的FPGA实现[J].电子技术应用,2011,37(7):29-31,35. |
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| 作者姓名： | 刘正平 夏威 何子述 |
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| 作者单位： | 电子科技大学电子工程学院,四川成都,611731 |
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| 摘 要： | 基于FPGA芯片Stratix Ⅱ EP2S60F672C4设计实现了数字基带预失真系统中的环路延迟估计模块.该模块运用了一种环路延迟估计新方法,易于FPGA实现.同时,在信号失真的情况下也能给出正确的估计结果.Modelsim SE 6.5c的时序仿真结果和SignalTaps Ⅱ的硬件调试结果验证了模块的有效性.
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| 关 键 词： | 功率放大器 数字基带预失真 相关 环路延时估计 FPGA |
An FPGA implementation of loop delay estimation in digital predistortion system |
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| Liu Zhengping,Xia Wei,He Zishu.An FPGA implementation of loop delay estimation in digital predistortion system[J].Application of Electronic Technique,2011,37(7):29-31,35. |
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| Authors: | Liu Zhengping Xia Wei He Zishu |
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| Abstract: | Based on FPGA chip Stratix Ⅱ EP2S60F672C,this paper designed and implemented a loop-delay estimation model in predistortion system.This model used a novel method of estimate the loop-delay,which is easy to implement in FPGA,and can give the right loop-delay estimation value under the condition of signal distortion.The timing simulation result of Modelsim SE 6.5c and hardware debugging result of SignalTap Ⅱ verified the valid of the model designed in this paper. |
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| Keywords: | power amplifier(PA) digital predistortion(DPD) correlation loop-delay estimation FPGA |
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