片上网络互连拓扑综述

随着器件、工艺和应用技术的不断发展，片上多处理器已经成为主流技术，而且片上多处理器的规模越来越大、片内集成的处理器核数目越来越多，用于片内处理器核及其它部件之间互连的片上网络逐渐成为影响片上多处理器性能的瓶颈之一。片上网络的拓扑结构定义网络内部结点的物理布局和互连方法，决定和影响片上网络的成本、延迟、吞吐率、面积、容错能力和功耗等，同时影响网络路由策略和网络芯片的布局布线方法，是片上网络研究中的关键之一。对比了不同片上网络的拓扑结构，分析了各种结构的性能，并对未来片上网络拓扑研究提出建议。

Survey on the Networks-on-Chip Interconnection Topologies

Along with the development of device, process and application technology, chip multiprocessor is becoming the mainstream technology. As the scale of chip multiprocessor as well as the number of integrated on-chip cores is getting larger and larger, the network-on-chip, which is dedicated to the interconnection and communication among on-chip cores and other components, is becoming one of the performance bottlenecks of chip multiprocessor. hhe topology of network-on-chip defines the physical layouts and the interconnection patterns of network nodes,determines the cost,latency, throughput, area, fault tolerance and power of network-on-chip, and impacts on the network routing policies, theplacement and routing designs of network chips. Therefore, the topology is one of the key technologies of network-on-chips. The paper compared various topological structures of network-on-chips in brief , analyzed their performances, and proposed recommendations for future research on the topology of network-on-chip.