| FPGA和USB2.0双工接口设计 |
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| 引用本文： | 王燕燕,刘勇,黄鲁. FPGA和USB2.0双工接口设计[J]. 自动化与仪表, 2012, 27(2): 45-48 |
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| 作者姓名： | 王燕燕 刘勇 黄鲁 |
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| 作者单位： | 中国科学技术大学电子科学与技术系集成电路实验室,合肥,230027 |
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| 摘 要： | 为了实现FPGA与USB2.0之间稳定快速的数据传输,该设计利用USB2.0接口芯片CY7C68013的Slave FIFO模式,采用时分复用的方法设计了一种双向数据接口。在FPGA端,持续把从USB OUT FIFO读出的数据回写到USB IN FIFO,以实现系统的自环测试。该设计已被应用到超宽带(UWB)无线系统中,结果表明本接口工作稳定,数据传输准确,平均速率12Mb/s。
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| 关 键 词： | 现场可编程门阵列 USB2.0 CY7C68013 Slave FIFO模式 Verilog HDL 双工接口 |
Design of Duplex Interface Between FPGA and USB2.0 |
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| WANG Yan-yan , LIU Yong , HUANG Lu. Design of Duplex Interface Between FPGA and USB2.0[J]. Automation and Instrumentation, 2012, 27(2): 45-48 |
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| Authors: | WANG Yan-yan LIU Yong HUANG Lu |
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| Affiliation: | (Department of Electronic Science and Technology,IC Lab,University of Science and Technology of China,Hefei 230027,China) |
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| Abstract: | In order to accomplish the high-speed data transportation between the FPGA and the USB2.0,The system implement a bi-directional interface which works in the Slave FIFO mode of USB2.0 interface chip CY7C68013 and using the time division multiplexing mechanism.After the self-loop testing by writing data continuously from OUT FIFO to IN FIFO of USB under the control of the FPGA,this design has been applied to the ultra-wideband(UWB)wireless systems.The results show that the interface works stably and transfers data accurately,its average rate is 12Mb/s. |
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| Keywords: | FPGA USB2.0 CY7C68013 Slave FIFO mode Verilog HDL duplex interface |
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