| 基于FPGA的数字锁相环的研究与实现 |
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| 引用本文： | 侯卫民,JIANG Jinghong,张骋,CAI Huizhi.基于FPGA的数字锁相环的研究与实现[J].微计算机应用,2008,29(8). |
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| 作者姓名： | 侯卫民 JIANG Jinghong 张骋 CAI Huizhi |
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| 作者单位： | 中国科学院声学所,北京,100190;中国科学院研究生院,北京,100080 |
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| 摘 要： | 介绍了当前广泛应用的数字锁相环的原理和基于FPGA的设计方法。针对在数字锁相环应用中,当滤波器K值较小时存在的相位抖动问题,提出了一种锁定检测模块的设计,通过仿真验证,该设计能够有效地抑制锁定状态下的相位抖动。
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| 关 键 词： | FPGA 数字锁相环 锁定检测模块 相位调整步长 |
Design on Digital Phase Locked Loop Based on FPGA |
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| HOU Weimin,JIANG Jinghong,ZHANG Cheng,CAI Huizhi.Design on Digital Phase Locked Loop Based on FPGA[J].Microcomputer Applications,2008,29(8). |
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| Authors: | HOU Weimin JIANG Jinghong ZHANG Cheng CAI Huizhi |
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| Affiliation: | HOU Weimin1,2,JIANG Jinghong1,2,ZHANG Cheng1,2,CAI Huizhi1 |
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| Abstract: | An all digital phase locked loop based on FPGA is presented.Compared with the method once widely used, a new module-phase- locked detector is proposed, which can deal with the problem of phase jitter.Key technology and implementation of the circuit is discussed and simulated. |
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| Keywords: | FPGA phase-locked loop phased-locked detector phasing adjustment step |
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