Managing Data Placement in Memory Systems with Multiple Memory Controllers |
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Authors: | M Awasthi D Nellans K Sudan R Balasubramonian A Davis |
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Affiliation: | 1. School of Computing, University of Utah, Salt Lake City, UT, USA 2. FusionIO, Cottonwood Heights, UT, USA
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Abstract: | Modern processors such as Tilera’s Tile64, Intel’s Nehalem, and AMD’s Opteron are migrating memory controllers (MCs) on-chip,
while maintaining a large, flat memory address space. This trend to utilize multiple MCs will likely continue and a core or
socket will consequently need to route memory requests to the appropriate MC via an inter- or intra-socket interconnect fabric
similar to AMD’s HyperTransportTM, or Intel’s Quick-Path InterconnectTM. Such systems are therefore subject to non-uniform memory access (NUMA) latencies because of the time spent traveling to
remote MCs. Each MC will act as the gateway to a particular region of the physical memory. Data placement will therefore become
increasingly critical in minimizing memory access latencies. Increased competition for memory resources will also increase
the memory access latency variation in future systems. Proper allocation of workload data to the appropriate MC will be important
in decreasing the variation and average latency when servicing memory requests. The allocation strategy will need to be aware
of queuing delays, on-chip latencies, and row-buffer hit-rates for each MC. In this paper, we propose dynamic mechanisms that
take these factors into account when placing data in appropriate slices of physical memory. We introduce adaptive first-touch
page placement, and dynamic page-migration mechanisms to reduce DRAM access delays for multi-MC systems. We also introduce
policies that can handle data placement in memory systems that have regions with heterogeneous properties. The proposed policies
yield average performance improvements of 6.5% for adaptive first-touch page-placement, and 8.9% for a dynamic page-migration
policy for a system with homogeneous DRAM DIMMs. We also show improvements in systems that contain DIMMs with different performance
characteristics. |
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