Feig快速DCT算法及其处理器的体系结构设计

离散余弦变换是ＪＰＥＧ和ＭＰＥＧ中的关键技术之一。当前ＭＰＥＧ的普遍应用是在解码中使用，一个解码的例子是ＶＣＤ，ＩＤＣＴ是静止／运动补偿帧解码的关键部分。为了要得到较好的性能，ＩＤＣＴ通常被硬件逻辑实现而嵌入产品中，但该方法有一个缺陷。那就是ＩＤＣＴ的硬件逻辑实现不能完成ＭＰＥＧ所需要的其它功能，如音频解码，视频／音频的比特流可变长度解码等等。文中提出的Ｆｅｉｇ快速ＤＣＴ算法的并行顺序指令流实现Ｉ

THE FEIG FAST DCT ALGORITHM AND ITS PROCESSOR ARCHITECTURE DESIGN

Discrete cosine transform(DCT) is a key element in the JPEG and MPEG standards. The current and projected popular usage of MPEG is for decoding applications. An example of decoding application is the video\|CD(VCD) in which inverse discrete cosine transform(IDCT) is a key element for the decompression of still/motion\|compensated video frames. It is indicated that IDCT embedded in products is performed by hard\|wired logic for performance reason. The approach has the drawback that the hard\|wired logic cannot help in other functionalities required in MPEG such as audio decoding, variable length decoding of video/audio bit stream, etc.. It is proposed that by executing the very efficient Feig IDCT algorithm using a processor architecture that performs parallel execution of sequential instruction streams, the above MPEG requirements can be satisfied. The proposed processor requires less hardware resources than the dedicated hard\|wired approach and the surplus computational power can also be used for audio decoding and variable length decoding of video/audio bit streams, etc..