一个支持多分支循环最优执行的VLIW体系结构

本首先提出一个能够支持多分支循环程序最优执行的ＶＬＩＷ体系结构模型，然后在这个模型的基础上设计了一个新的主要用于数字信号处理及图象处理应用领域的单片体系结构－ＵＲＰＲ－２。在这个体系结构中，属于不同路径和不同循环体的多个分支操作可以在一个节拍内同时被执行，因此可以在更大范围内开发指讼级并行性，同时还提出了一个种叫作流水控制黑板的机制来支持条件分支操作。ＵＲＰＲ－２不仅能够以很高的速度执行只含有基

A VLIW ARCHITECTURE FOR OPTIMAL EXECUTION OF BRANCH-INTENSIVE LOOPS

We propose a VLIW architectural model for optimal execution of branch-intensive loops as well as a new single-chip architecture URPR-2 for digital signal and image processing based on this model. In this architecture the instructions belonging to different iterations and different paths can be executed simultaneously. Instruction level parallelism can be exploited in a wider scope as multi-branching can be processed in each machine cycle. A mechanism called the pipeline control blackboard (PCBB) is also proposed to support conditional branches. The URPR2 can not only execute loops with basic block at high speed but also can run loops with conditional branches at a cost of reduced time and space occupancy.