基于2D Cache结构的H.264运动补偿访存带宽优化方法

H.264/AVC的运动补偿处理环节需要消耗大量的内存访问带宽,这成为制约其性能的关键因素.分析表明,如此巨大的带宽消耗具体来自5个方面:像素数据的重复读取、地址对齐、突发访问、SDRAM页切换和内存竞争冲突.提出一种基于2D Cache结构的运动补偿带宽优化方法,充分利用像素的重用以减少数据的重复读取.同时通过结合数据在SDRAM中映射方式的优化,将众多短而随机的访问整合为地址对齐的突发访问,并减少了访问过程中页切换的次数.此外还提出了访存的组突发访问模式,以解决SDRAM竞争冲突所引入的开销.实验结果表明采用上述优化设计后,运动补偿的访存带宽降低了82.9～87.6%,同现存优化效率较高的方法相比,带宽进一步减少了64%～87%.在达到相同带宽减少幅度的前提下,所提出的新方法比传统Cache结构电路面积减少91%.该方法目前已在一款多媒体SoC芯片设计中实际应用.

A 2D-Cache Based Memory Bandwidth Optimization Method for H.264 MotionCompensation

Motion compensation(MC) consumes a lot of external memory bandwidth during H.264/AVC video decoding,which becomes a significant bottleneck of high definition(HD) H.264/AVC video codec design.Analytical results show that such significant bandwidth consumption comes from five parts:pixel data reload,address alignment,burst access,SDRAM page precharge active and conflict memory accesses.In view of this,a 2D-cache based MC bandwidth optimization method is proposed.By exploiting pixel data reuse,such optimization method avoids large numbers of data reloading.Through the combination with SDRAM data mapping optimization,it integrates many short random accesses to some address aligned burst accesses,and at the same time reduces the page precharge active frequency.In addition,a memory access group burst mode is proposed to reduce the bandwidth consumption caused by the conflict SDRAM access.Experimental results show that the new method reduces 82.9%-87.6% of the MC memory bandwidth,and it demonstrates a further reduction of 64%-87% of the bandwidth consumption compared with some existing high optimization efficiency methods.Provided the same amount of bandwidth reduction,the circuit area of the new method is reduced by 91% compared with the traditional cache architecture.The method proposed in this paper has been applied in a multimedia SoC chip.