吞吐量和延时约束下的片上通信结构的Pareto空间优化

SoC中各IP核之间的互连结构是决定片上系统性能的关键因素.近年来,片上互连通信结构的配置与优化成为SoC通信综合的研究重点和热点,而已有方法优化SoC互连通信结构的仿真速度较慢,支持设计自动化的能力较差,使用的单目标优化算法无法解决多个性能目标之间的冲突.针对以上不足提出了吞吐量和延时约束下的片上互连通信结构的自动配置与优化的方法,该方法提出了片上总线互连通信结构模板,使用事务级通信仿真和多目标演化算法,探索吞吐量和延时约束下的多目标Pareto空间.与已有的先进Srinivasan方法相比,该方法的吞吐量提高10%,传输延迟降低17%,有效提高了SoC互连通信结构的优化质量.

Pareto Space Optimization for Throughput and Delay Constrained on-Chip-Communication Architectures

The performance of SoC depends mainly on the interconnect architecture of IP cores.Recently,the configuration and optimization of on-chip-communication architectures become hot and popular,while existing methods still have some disadvantages of low simulation speed and poor design space exploration.Besides,mostly used single objective optimization cannot resolve the conflict of multiple performance objectives.An automatic Pareto space optimization approach is put forward for throughput and delay constrained on-chip-communication architectures,which uses on-chip communication architecture template,transaction level communication simulation and evolutionary multi-objective optimization algorithm to explore the Pareto space with throughput and delay constraints.Experiments show that the approach effectively improves the quality and the speed of optimizing SoC communication architecture,which improves the throughput by 10% and reduce the transfer delay by 17% compared with that of Srinivasan.