基于SystemC的SoC行为级软硬件协同设计

针对目前SoC设计中存在的软硬件协同验证的时间瓶颈问题，提出了一种使用系统建模语言SystemC对SoC进行总线周期精确行为级建模的方法，采用该方法构建SoC芯片总线周期精确行为级模型进行前期验证。该模型基于32位RISC构建，并可配置其它硬件模块。实验结果表明：模型完全仿真实际硬件电路，所有的接口信号在系统时钟的任一时刻被监测和分析，很大程度地提高了仿真速度，并且可以在前期作系统的软硬件协同仿真和验证，有效地缩短了目前SoC芯片设计中在RTL级作软硬件协同仿真验证时的时间开销。

SoC Behavior Level HW/SW Co-design and Co-verification Based on SystemC

With respect to the software and hardware co-verification bottleneck of SoC design, a bus-cycle accurate method is presented based on SystemC reference behavior modeling and the model is realized. The model is based on 32 bits RISC, and other modules can be configured. All the modules are triggered through the clock. The result of the test is that the model can simulate the real hardware circuit accurately, and the signal of the conjunction can be monitored at any time; the speed of the simulation is increased greatly and the time consumption is much less than that of the RTL level co-verification in the SoC design.