| 快速全数字逐次逼近寄存器延时锁定环的设计 |
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| 引用本文： | 徐太龙,薛峰,蔡志匡,郑长勇.快速全数字逐次逼近寄存器延时锁定环的设计[J].计算机工程,2014(4):262-268. |
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| 作者姓名： | 徐太龙 薛峰 蔡志匡 郑长勇 |
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| 作者单位： | [1]合肥学院电子信息与电气工程系,合肥230601 [2]安徽三联学院信息与通信技术系,合肥230601 [3]东南大学国家专用集成电路系统工程技术研究中心,南京210096 [4]安徽建筑大学电子与信息工程学院,合肥230601 |
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| 基金项目： | 基金项目：安徽省高等学校省级自然科学研究基金资助项目（KJ2013A071）;安徽省高校优秀青年人才基金资助项目（2012SQRL013ZD）. |
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| 摘 要： | 全数字延时锁定环在现代超大规模系统芯片集成中具有重要的作用,用于解决时钟偏差和时钟生成问题。传统的全数字逐次逼近寄存器延时锁定环存在谐波锁定、死锁和锁定时间比理论时间长的问题。为此,通过改进逐次逼近寄存器的电路结构,采用可复位数控延时线,设计一种改进型宽范围全数字逐次逼近延时锁定环,以解决谐波锁定和死锁问题。基于中芯国际0.18μm CMOS数字工艺,实现一个6位全数字逐次逼近寄存器延时锁定环。仿真结果表明,最长锁定时间为6个输入时钟周期,验证了所提方法的正确性。
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| 关 键 词： | 延时锁定环 谐波锁定 时钟偏差 死锁 锁定时间 逐次逼近寄存器 |
Design of Fast All Digital Successive Approximation Register Delay-locked Loop |
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| XU Tai-long,XUE Feng,CAI Zhi-kuang,ZHENG Chang-yong.Design of Fast All Digital Successive Approximation Register Delay-locked Loop[J].Computer Engineering,2014(4):262-268. |
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| Authors: | XU Tai-long XUE Feng CAI Zhi-kuang ZHENG Chang-yong |
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| Affiliation: | 1. Department of Electronic Information and Electrical Engineering, Hefei University, Hefei 230601, China; 2. Department of Information and Communication Technology, Anhui Sanlian University, Hefei 230601, China; 3. National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China; 4. School of Electronic and Information Engineering, Anhui Jianzhu University, Hefei 230601, China) |
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| Abstract: | All digital delay-locked loops play an important role in modem day very large scale system-on-chips, which are widely used to solve the problems of clock skew and clock generation. Conventional all digital Successive Approximation Register Delay-locked Loop （SARDLL） have problems of harmonic lock, dead-lock and lock time longer than the theoretical value. To solve these problems, a wide-range all digital SARDLL which has no harmonic lock, dead lock and has theoretical lock time is proposed, by improving the circuit structure of conventional successive approximation register and adopting the resettable digital-controlled delay line. Based on the SMIC 0,18 Ixm CMOS, a 6 bit improved all digital SARDLL is implemented. The transistor-level post-layout simulation results show that the longest lock time is 6 input clock cycles and the proposed SARDLL is validated. |
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| Keywords: | delay-locked loop harmonic lock clock skew dead lock lock time Successive Approximation Register（SAR） |
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