| 一种低硬件开销的高级加密标准设计 |
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| 引用本文： | 陈海进,景为平.一种低硬件开销的高级加密标准设计[J].计算机工程,2005,31(20):165-167. |
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| 作者姓名： | 陈海进 景为平 |
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| 作者单位： | 南通大学江苏省专用集成电路设计重点实验室,南通226007 |
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| 基金项目： | 上海市科委集成电路设计创新基金资助项目（027062011） |
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| 摘 要： | 在智能卡、PDA等便携式设备中，希望使用面积小的密码芯片。通过对AES算法进行结构优化，有效地减小了硬件实现时的开销。使用Verilog HDL语言设计并在Altera APEX20K器件中验证通过，设计集成了加密／解密模式及所有3种密钥长度，为进一步的VLSI实现提供了FPGA原形验证。
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| 关 键 词： | 高级加密标准 CMOS 逻辑综合 FPGA |
| 文章编号： | 1000-3428（2005）20-0165-03 |
| 收稿时间： | 01 12 2005 12:00AM |
| 修稿时间： | 2005-01-12 |
Design of Low Hardware-cost AES |
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| CHEN Haijin, JING Weiping.Design of Low Hardware-cost AES[J].Computer Engineering,2005,31(20):165-167. |
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| Authors: | CHEN Haijin JING Weiping |
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| Affiliation: | Jiangsu Provincial Key Lab of ASIC Design, Nantong University, Nantong 226007 |
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| Abstract: | Small area is required for cipher chips used in portable devices such as smart card and PDA etc. The requirement for hardware resource is dramatically decreased by careful optimization of the AES algorithm. The optimized AES architecture is described by Verilog HDL and implemented with Altera APEX20K device. The validated FPGA prototype integrates both the encryption and decryption modes and all the three kinds of key length, which is suitable for the future VLSI implementation of the AES. |
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| Keywords: | AES CMOS Logic synthesis FPGA |
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