| 高性能并行Turbo译码器的VLSI设计 |
| |
| 引用本文： | 陈绪斌,曹嘉麟,陈赟,曾晓洋.高性能并行Turbo译码器的VLSI设计[J].计算机工程,2012,38(23):255-258. |
| |
| 作者姓名： | 陈绪斌 曹嘉麟 陈赟 曾晓洋 |
| |
| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室,上海,201203 |
| |
| 基金项目： | 国家"863"计划基金资助项目，国家科技重大专项基金资助项目"新一代宽带无线移动通讯网" |
| |
| 摘 要： | 提出一种高度并行的Turbo译码器。该译码器包含32个并行的基-4子译码器，采用改进的滑窗译码流程和存储单元划分方案，使吞吐率最高提升43.2%。在SMIC 0.13 μm工艺下，该译码器包含194万等效门，在294 MHz时钟频率和5.5次迭代下，吞吐率可达 1.19 Gb/s，满足4G移动通信标准LTE-Advanced的峰值吞吐率要求。
|
| 关 键 词： | Turbo码 译码器 并行结构 基-4 4G移动通信 |
| 收稿时间： | 2012-03-12 |
VLSI Design of High Performance Parallel Turbo Decoder |
| |
| CHEN Xu-bin
,
CAO Jia-lin
,
CHEN Yun
,
ZENG Xiao-yang.VLSI Design of High Performance Parallel Turbo Decoder[J].Computer Engineering,2012,38(23):255-258. |
| |
| Authors: | CHEN Xu-bin CAO Jia-lin CHEN Yun ZENG Xiao-yang |
| |
| Affiliation: | (State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China) |
| |
| Abstract: | This paper presents a highly-parallel Turbo decoder architecture. It utilizes 32-parallel radix-4 component decoders and its throughput is increased by 43.2% at most with modified sliding window and memory partition scheme. The proposed decoder is implemented in SMIC 0.13 μm technology, which has 1.94 M equivalent gate counts and achieves 1.19 Gb/s running at 294 MHz with 5.5 iterations. It meets the peak data rate requirement of 4G mobile communication standard LTE-Advanced. |
| |
| Keywords: | Turbo code decode parallel architecture radix-4 4G mobile communication |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
| 点击此处可从《计算机工程》浏览原始摘要信息 |
|
点击此处可从《计算机工程》下载全文 |
