FPGA互连测试中的反馈桥接故障覆盖问题

现场可编程门阵列(FPGA)内部资源众多,其中互连资源出现故障的概率远远高于片内其他资源,而在以往许多互连测试研究中,所生成的测试配置存在无法覆盖反馈桥接故障的难题,所以较难有测试配置实现故障列表的100%覆盖。因此通过约束桥接故障只发生在单个查找表(LUT)内的信号线上,并结合单项函数,对反馈桥接故障模型进行优化改进,从根本上解决难题；然后对优化后的反馈桥接故障设置相应的约束条件,再使用布尔可满足性理论(SAT)生成满足约束条件的测试配置。采用优化后的故障模型对ISCAS"89基准电路进行了测试配置生成实验,结果表明生成的测试向量解决了反馈桥接故障的覆盖难题,并且在实现故障列表的100%覆盖下,优化后的故障模型所需要的测试配置数最少。

The coverage problem of Feedback-bridging fault in the FPGA interconnection test

There are many internal resources in Field Program Gate Array (FPGA), among which the failure probability of interconnect resources is much higher than that of other on-chip resources. However, in many researches on interconnect testing, the generated test configurations are hardly able to cover the feedback-bridging faults, so it was rare to achieve 100% coverage of interconnection fault list. Therefore, the feedback bridge fault model is optimized by constraining the bridge faults within a single look-up table (LUT) and using single-term functions, so as to fundamentally solve the problem. Then, the corresponding constraints are set for the optimized feedback bridge faults, and the test configurations meeting the constraints are generated using the Boolean Satisfiability theory (SAT). Finally, the test configuration generation experiment of the ISCAS"89 benchmark circuit is carried out, and the experimental results show that the generated test vectors not only solve the coverage problem of feedback-bridging faults, but also achieve 100% coverage of the fault list with the minimum configuration times.