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基于向量引用Platform-Oblivious内存连接优化技术
引用本文:张延松,张宇,王珊.基于向量引用Platform-Oblivious内存连接优化技术[J].软件学报,2018,29(3):883-895.
作者姓名:张延松  张宇  王珊
作者单位:中国人民大学数据工程与知识工程教育部重点实验室, 北京 100872;中国人民大学信息学院, 北京 100872;中国人民大学中国调查与数据中心, 北京 100872,国家卫星气象中心, 北京 100081,中国人民大学数据工程与知识工程教育部重点实验室, 北京 100872;中国人民大学信息学院, 北京 100872
基金项目:国家自然科学基金项目(61732014,61772533);国家高技术研究发展计划(863计划)项目(2015AA015307);中央高校基本科研业务费专项资金项目(16XNLQ02)
摘    要:以MapD为代表的图分析数据库系统通过GPU、Phi等新型众核处理器来支持高性能分析处理,在面向复杂数据模式时连接操作仍然是重要的性能瓶颈.近年来,异构处理器逐渐成为高性能计算的主流平台,内存连接性能的研究从多核CPU平台扩展到新兴的众核处理器,但众多的研究成果并未系统地揭示连接算法性能、连接数据集大小、硬件架构之间的内在联系,难以为未来异构处理器平台的数据库提供连接平台优化选择策略.本文以面向多核CPU、Xeon Phi、GPU处理器平台的内存连接优化技术为目标,通过优化内存哈希表设计,实现以向量映射替代哈希映射操作,消除哈希代价对内存连接算法的影响,从而更加准确地测量内存连接算法在多核CPU的cache大小、Xeon Phi的cache大小、Xeon Phi的并发多线程、GPU的SIMT(单指令多线程)机制等硬件相关因素影响下的性能特征.实验结果表明,缓存与并发多线程机制是提高内存连接算法性能的重要影响因素.缓存机制对于满足cache大小的连接操作具有性能优势,而GPU的并发多线程机制则在较大表的连接操作中具有较高的性能,Xeon Phi则在满足其L2 cache大小的连接操作中具有最高性能.实验结果揭示了内存连接操作性能与异构处理器硬件特性的联系,为未来异构处理器平台内存数据库查询优化器提供了优化策略.

关 键 词:内存连接操作  哈希连接  向量映射  异构处理器平台
收稿时间:2017/7/31 0:00:00
修稿时间:2017/9/5 0:00:00

Vector Referencing Oriented Platform-Oblivious In-Memory Join Optimization Technique
ZHANG Yan-Song,ZHANG Yu and WANG Shan.Vector Referencing Oriented Platform-Oblivious In-Memory Join Optimization Technique[J].Journal of Software,2018,29(3):883-895.
Authors:ZHANG Yan-Song  ZHANG Yu and WANG Shan
Affiliation:Key Laboratory of Data Engineering and Knowledge Engineering(Renmin University), Ministry of Education, Beijing 100872;School of Information, Renmin University of China, Beijing 100872;National Survey Research Center at Renmin University of China, Beijing 100872,National Satellite Meteorological Centre, Beijing 100081, China and Key Laboratory of Data Engineering and Knowledge Engineering(Renmin University), Ministry of Education, Beijing 100872;School of Information, Renmin University of China, Beijing 100872
Abstract:The representative graph analysis database such as MapD employed the emerging manycore architecture GPU and Phi processors to support high performance analytical processing, the join operation is still the performance bottleneck when facing complex data schemas. In recent years, the heterogeneous processors come to be main-stream high performance computing platforms, the researches of in-memory join performance extend the focuses from multicore to the emerging manycore platforms. But the rich approaches have not discovered the inner relationships among join algorithm performance, join dataset size, and hardware architectures, and cannot provide sufficient join selection strategies for databases on the future heterogeneous processor platforms. This paper targets at in-memory join optimization techniques on multicore, Xeon Phi and GPU processor platforms, by optimizing hash table design, we use vector mapping instead of hash mapping to eliminate the hashing overhead effects for performance, so that we can accurately measure the in-memory join performance characteristics influenced by hardware factors such as multicore cache size, Xeon Phi cache size, Xeon Phi simultaneous multi-threading mechanism, GPU SIMT(Single Instruction Multiple Threads) mechanism. The experimental results show that caching and simultaneous massive-threading mechanism are key factors to improve in-memory join algorithm performance. Caching mechanism performs well for cache fit join operations, the simultaneous massive-threading mechanism of GPU does well for big table joins, Xeon Phi achieves the highest performance for L2 cache fit joins. The experimental results exploit the relationship between in-memory join performance and heterogeneous processor hardware features, and provide optimization policy for in-memory database query optimizer on future heterogeneous processor platforms.
Keywords:in-memory join operation  hash join  vector mapping  heterogeneous processor platforms
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