数据中心中DVFS对程序性能影响模型的设计

数据中心以可接受的成本承载着超大规模的互联网应用.数据中心的能源消耗直接影响着数据中心的一次性建造成本和长期维护成本，是数据中心总体持有成本的重要组成部分.现代的数据中心普遍采用DVFS（Dynamic Voltage Frequency Scaling，动态电压频率调节）来提升单节点的能耗表现.但是，DVFS这一类机制同时影响应用的能源消耗和性能，而这一问题尚未被深入探索.本文专注于DVFS机制对应用程序性能的影响，提出了一个分析模型用来量化地刻画应用程序的性能同处理器频率之间的关系，可以预测程序在任意频率下的性能.具体来说，依据执行时访问内存子系统资源的不同，本文把程序的指令为两部分：片上指令和片外指令，并分别独立建模.片上指令指仅需访问片上资源就可以完成执行的指令，其执行时间同处理器频率成线性关系；片外指令指需要访问主存的指令，其执行时间同处理器频率无关.通过上述划分和对每部分执行时间的分别建模，我们可以获得应用程序的执行时间同处理器频率之间的量化模型.我们使用两个不同的平台和SPEC 2006中的所有标准程序验证该模型，平均误差不超过1.34%.

Modeling the Impact of DVFS on Performance of Applications in Datacenter

Datacenters are built to house massive scale internet services at an affordable price. Both Op-ex (long-time operational expenditure) and Cap-ex (one-time construction costs) are directly impacted by datacenter power consumption. Thus, DVFS (Dynamic Voltage and Frequency Scaling) is widely adopted to improve per node energy efficiency. However, such schemes affect an application''s power consumption and performance simultaneously, which is well-known but not deeply explored so far. In this paper, we focus on the impact of DVFS onperformance of an applicationand propose an analytical model to quantitatively characterize the relationship between an application''s performance and a processor''s frequency, which can be leveraged to predict the performance of an application at any frequency. Specifically, according to different memory subsystem resources accessed, instructionsof an application are divided into two parts:on-chip instructions andoff-chip instructions, which can be modeled independently. On-chip instructions refer to instructions which only access on-chip resources, and the execution time of them is frequency-relevant and can be modeled using a linear function. Off-chip instructions stand for instructions accessing the main memory, their execution time is dominated by memory access latency and is frequency-irrelevant. By the division and modeling of the two parts, we can obtain a quantitative model between the execution time of an application and frequency of a processor. Evaluations using two different platforms and all benchmarks of SPEC 2006 show that the models thus obtained are very precise, with an average prediction error less than 1.34%.