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片上多核处理器Cache一致性协议优化研究综述
引用本文:胡森森,计卫星,王一拙,陈旭,付文飞,石峰.片上多核处理器Cache一致性协议优化研究综述[J].软件学报,2017,28(4):1027-1047.
作者姓名:胡森森  计卫星  王一拙  陈旭  付文飞  石峰
作者单位:北京理工大学 计算机学院, 嵌入式高性能计算实验室, 北京 100081,北京理工大学 计算机学院, 嵌入式高性能计算实验室, 北京 100081,北京理工大学 计算机学院, 嵌入式高性能计算实验室, 北京 100081,北京理工大学 计算机学院, 嵌入式高性能计算实验室, 北京 100081,北京理工大学 计算机学院, 嵌入式高性能计算实验室, 北京 100081,北京理工大学 计算机学院, 嵌入式高性能计算实验室, 北京 100081
基金项目:国家自然科学基金(61300010,613000011);中国科学院计算技术研究所计算机体系结构国家重点实验室开放课题资助.
摘    要:现代晶体管技术在单芯片上集成多个处理器已经成为现实.近年来,随着多核处理器集成核数的不断增加,高速缓存的一致性问题凸显出来,已成为多核处理器的性能瓶颈之一,亟待解决.本文介绍了片上多核处理器一致性问题的由来.总结了多核时代高速缓存一致性协议设计的关键问题,综述了近年来学术界对一致性的研究.从程序访存行为模式、目录组织结构、一致性粒度、一致性协议流量、目录协议的可扩展性等方面,阐述了近年来缓存一致性协议性能优化的方向.对目前片上多核处理器缓存一致性协议设计中存在的问题进行了讨论,并指出了未来进一步研究的方向.

关 键 词:片上多核处理器  缓存一致性协议  性能优化
收稿时间:2016/5/23 0:00:00
修稿时间:2016/8/18 0:00:00

Survey on Cache Coherence Protocol and Performance Optimization for Chip Multi-Processor
HU Sen-Sen,JI Wei-Xing,WANG Yi-Zhuo,CHEN Xu,FU Wen-Fei and SHI Feng.Survey on Cache Coherence Protocol and Performance Optimization for Chip Multi-Processor[J].Journal of Software,2017,28(4):1027-1047.
Authors:HU Sen-Sen  JI Wei-Xing  WANG Yi-Zhuo  CHEN Xu  FU Wen-Fei and SHI Feng
Institution:School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China,School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China,School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China,School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China,School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China and School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China
Abstract:Modern-day transistor technique enables the industry to integrate many cores on a single chip.As an increasing number of cores being integrated on a single chip, cache coherence has become an intractable issue as well as a bottleneck of performance.In this paper, the origin of cache coherence is carefully described.Further, this paper summarizes the key issue of cache coherence and reviews the study of decade in this field as entering the mulit-core era.From memory access, directory organiztion, coherence granularity, coherence traffic and scalability such five aspects, we present how to optimize cache coherence in recent researches.Finally, the potential challenges in current coherence protocol are discussed.We also point out the direction of future research.
Keywords:chip multi-processor  cache coherence protocol  performance optimization
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