基于VHDL与ECS的CA-D6驱动时序设计

简要介绍了高帧频摄像头CA-D6的图像传感器IA-D6的工作原理,分析了高帧频摄像头CA-D6采集图像的驱动工作时序。分析比较了进行时序设计的几种常用方法,着重介绍了如何利用XILINX综合工具ISE的两种输入设计方法VHDL（可视化硬件描述语言）和ECS（原理图编辑器）相结合来设计以及实现高帧频摄像头CA-D6的驱动时序,并给出了时序仿真结果。该设计已被应用到课题之中。

CA-D6 timing design based on VHDL & ECS

The work principle of image sensor IA-D6 in high frame rate CA-D6. High frame rate CA-D6 driving timing of acquiring image is analyzed. Several methods on timing design are compared and analyzed. In particular, high frame rate CA-D6 driving timing is designed and implemented by mixed designing method composed of ECS and VHDL which are input design methods embedded in FPGA/CPLD designing tool ISE. And CA-D6 driving timing emulation results are presented. The driving timing design of CA-D6 is applied in interrelated work successfully.