| 二维离散小波提升变换算法的并行结构设计 |
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| 引用本文： | 田宝华,李宝峰.二维离散小波提升变换算法的并行结构设计[J].计算机应用,2011,31(12):3366-3369. |
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| 作者姓名： | 田宝华 李宝峰 |
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| 作者单位： | 1. 国防科学技术大学 计算机学院,长沙 4100732. 国防科学技术大学 计算机学院， 长沙 410073 |
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| 摘 要： | 提出了一种二维离散小波提升变换（2DDWT）的2×2并行结构。该结构充分利用了2DDWT算法固有的行并行、列并行、行列并行的三种并行性，有效提高了算法执行速度，同时显著降低了硬件存储需求。处理N×N图像的时间为N2/4+N/2+1，系统存储需求为3N。FPGA实现结果证明了本设计的正确性和有效性。
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| 关 键 词： | 二维离散小波提升整数变换 并行结构 现场可编程门阵列 |
| 收稿时间： | 2011-05-25 |
| 修稿时间： | 2011-07-14 |
Parallel architecture for lifting-based 2DDWT algorithm |
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| TIAN Bao-hua,LI Bao-feng.Parallel architecture for lifting-based 2DDWT algorithm[J].journal of Computer Applications,2011,31(12):3366-3369. |
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| Authors: | TIAN Bao-hua LI Bao-feng |
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| Affiliation: | School of Computer, National University of Defense Technology, Changsha Hunan 410073,China |
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| Abstract: | A 2x2 parallel architecture for the lifting-based 2D Discrete Wavelet Transform (2DDWT) is presented. The architecture exploits three inherent parallelisms in 2DDWT - row parallel, column parallel and row-column parallel to improve the execution speed and reduce the memory requirement. The proposal takes N2/4+N/2+1 clocks to transform a N×N image while only 3N internal memory is required. The architecture is verified by simulation and implemented in a StratixⅡFPGA |
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| Keywords: | Discrete Wavelet Transform (DWT) parallel atchitecture Field Programmable Gate Array (FPGA) |
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