片上网络的低功耗编码方法研究

从编码的角度出发,对降低片上网络的互连线功耗的方法进行了分析和研究.通过在片上微网络中采用纠错编码降低互连线电压摆幅的方法,在保证可靠性的同时,降低了功耗,实现了可靠性与功耗的合理折中.采用避免串扰码有效地减少线间耦合,从而达到降低线间耦合功耗的效果.并对纠错码与避免串扰码相结合降低互连线功耗的方法进行了分析.采用0.13μm CMOS工艺对各种编码方案进行了功耗仿真,结果显示:几种方案中联合编码方案节省功耗的效果最为明显.

Coding schemes research for low power in NoC

In this paper, coding schemes to reduce the power of network interconnection in Network On Chip (NOC) were researched. By reducing the voltage swing on interconnects after using Error Correction Code (ECC), we could save the power without lowering the reliability requirement, and achieved a reasonable tradeoff between reliability and power. Crosstalk Avoidance Code (CAC) could be used to reduce the mutual inter-wire coupling capacitance and hence the energy dissipation between wires. Further more, the method to reduce interconnects power with joint ECC and CAC was analyzed. In the end, the power consumptions of coding schemes were simulated by 0.13 μm COMS technology and the results show that the joint code save the most power.