基于PCIe的多路传输系统的DMA控制器设计

为了避免PCIe传输过程中PIO写延时、主机与嵌入式处理系统交互次数过多等问题对于传输带宽的影响，设计了一种基于命令缓冲机制的直接存储访问（DMA）控制器以提高传输带宽利用率。采用FPGA端内部设置命令缓冲区的方式，使得DMA控制器可以缓存PC端的数据传输请求，FPGA根据自身需求动态地访问PC端存储空间，增强了传输灵活性；同时，提出一种动态拼接的DMA调度方法，通过合并相邻存储区访问请求的方式，进一步减少主机与硬件的交互次数和中断产生次数。系统传输速率测试实验中，DMA写最高速率可达1631 MB/s，DMA读最高速率可达1582 MB/s，带宽最大值可达PCIe总线理论带宽值的85.4%；与传统PIO方式的DMA传输方法相比，DMA读带宽提升58%，DMA写带宽提升36%。实验结果表明，本设计能够有效提升DMA传输效率，明显优于PIO方式。

Design of DMA controller for multi-channel transmission system based on PCIe

To reduce the impact of Programmed I/O (PIO) write latency in PCI express (PCIe) transmission process, too many times of interaction between the host and the embedded processing system and other issues on transmission bandwidth, a Direct Memory Access (DMA) controller based on command buffering mechanism was designed to improve the transmission bandwidth utilization. Using the internal command buffer of the Field-Programmable Gate Array (FPGA), the DMA controller could cache the data transfer request of the PC. The FPGA could dynamically access the storage space of the PC according to its own requirements and enhance the transmission flexibility. At the same time, a dynamic mosaic DMA scheduling method was proposed to reduce the times of host-to-hardware interaction and interrupt generation by merging the access requests of adjacent storage areas. In the system transmission rate test, the maximum write speed of DMA was 1631 MB/s, the maximum rate of DMA read was up to 1582 MB/s, the maximum of bandwidth was up to 85.4% of the theoretical bandwidth of PCIe bus. Compared with the traditional PIO mode DMA transfer method, DMA read bandwidth increased by 58%, DMA write bandwidth increased by 36%. The experimental results show that the proposed design can effectively improve the DMA transfer efficiency, and is significantly better than PIO method.