| 基于FPGA的CRC并行算法研究与实现 |
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| 引用本文： | 常天海,胡鉴.基于FPGA的CRC并行算法研究与实现[J].微处理机,2010,31(2):45-48. |
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| 作者姓名： | 常天海 胡鉴 |
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| 作者单位： | 华南理工大学电子与信息学院,广州,510640 |
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| 摘 要： | 循环冗余校验(CRC)算法广泛应用于通信领域以提高数据传输的可靠性.针对通信过程中常用的CRC校验,介绍了CRC的编码和解码原理,分析了CRC的经典算法的实现过程,并在此基础上提出了基于FPGA的CRC并行处理算法.采用VHDL语言对算法完成建模与实现,并以Altera公司开发的EDA工具QuartusII8.0作为编译、仿真平台进行了仿真验证.电路的综合结果表明,该方法具有更少的资源占用量和更高的工作效率.
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| 关 键 词： | 并行编码器 循环冗余校验 现场可编程门阵列 硬件描述语言 |
Applicating Research of CRC Parallel Algorithm Based on FPGA |
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| CHANG Tian-hai,HU Jian.Applicating Research of CRC Parallel Algorithm Based on FPGA[J].Microprocessors,2010,31(2):45-48. |
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| Authors: | CHANG Tian-hai HU Jian |
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| Affiliation: | CHANG Tian-hai,HU Jian(School of Electronic , Information Engineering of the South China University of Technology,Guangzhou 510640,China) |
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| Abstract: | Cyclic Redundancy Check(CRC) algorithm is widely used in communication fields to improve the reliability for data transmission.According to the CRC checksum principle that commonly used in the communication process,this paper introduce the principle of CRC calculation.After having analyzed the classical CRC algorithm implementation process,this article introduces a fast parallel CRC calculation based on FPGA.The QuartusII8.0 of Altera Inc is chosen as a compiler,simulation platform,the modeling and realizat... |
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| Keywords: | Parallel encoder CRC FPGA VHDL |
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