High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications |
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Authors: | Athanasios P Kakarountas Haralambos Michail Athanasios Milidonis Costas E Goutis George Theodoridis |
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Affiliation: | (1) VLSI Design Laboratory, University of Patras, Patras, GREECE;(2) Electronics Laboratory, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, GREECE |
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Abstract: | Hash functions are special cryptographic algorithms, which are applied wherever message integrity and authentication are critical.
Implementations of these functions are cryptographic primitives widely used in common cryptographic schemes and security protocols
such as Internet Protocol Security (IPSec) and Virtual Private Network (VPN). In this paper, a novel FPGA implementation of
the Secure Hash Algorithm 1 (SHA-1) is proposed. The proposed architecture exploits the benefits of pipeline and re-timing
of execution through pre-computation of intermediate temporal values. Pipeline allows division of the calculation of the hash
value in four discreet stages, corresponding to the four required rounds of the algorithm. Re-timing is based on the decomposition
of the SHA-1 expression to separate information dependencies and independencies. This allows pre-computation of intermediate
temporal values in parallel to the calculation of other independent values. Exploiting the information dependencies, the fundamental
operational block of SHA-1 is modified so that maximum operation frequency is increased by 30% approximately with negligible
area penalty compared to other academic and commercial implementations. The proposed SHA-1 hash function was prototyped and
verified using a XILINX FPGA device. The implementation’s characteristics are compared to alternative implementations proposed
by the academia and the industry, which are available in the international IP market. The proposed implementation achieved
a throughput that exceeded 2,5 Gbps, which is the highest among all similar IP cores for the targeted XILINX technology. |
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Keywords: | Security hash function hardware implementation high-speed performance FPGA |
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