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The iCore 520-MHz synthesisable CPU core |
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| Authors: | Richardson N Lun Bin Huang Hossain R Lewis J Zounes T Soni N |
| Affiliation: | STMicroelectronics, San Diego, CA, USA; |
| Abstract: | A new implementation of the ST20-C2 CPU architecture involves an eight-stage pipeline with hardware support to execute up to three instructions per cycle. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core. |
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