基于循环的指令高速缓存访问预测方法

为了减少高速缓存访问功耗,提出了一种针对循环的基于历史访问路径的指令高速缓存访问预测方法。该方法以循环作为高速缓存访问路预测行为开启的先决条件,通过指令高速缓存的历史访问路径训练预测器。当循环体再次进入时选择对应的访问路径预测器,获取目标指令高速缓存的路进行访问,降低访问功耗。并进一步提出多路径路预测方法,以得到更高的预测准确率。基于Powerstone测试基准的实验结果表明,该预测方法能达到99%的预测准确率。相比传统的指令高速缓存,使用本方法的高速缓存可平均降低65%的访问功耗,仅增加约0.2%的平均指令高速缓存访问周期。

Loop based trace way prediction for instruction cache

This paper proposed a new scheme of way prediction, named loop based trace way prediction, for instruction cache, to decrease the access power. The scheme made loop the premise of starting way prediction. By recording the trace of cache access when it encountered a loop, it could predict the way when getting in the same loop. Also made a research on multiple-trace way prediction scheme to get a better hit rate. Experiment results from Powerstone show this scheme can get a hit rate of 99%. On average it can decrease 65% power dissipation compared to conventional set-associative cache, and increase only 0. 2% the time to access cache.