FPGA的宽带步进频率信号源设计

介绍了基于FPGA和锁相频率合成器芯片ADF4350的宽带步进频率信号源的设计与实现方法。通过分析两种不同的实现方法，确定了以DDS输出的扫描频率控制锁相环鉴相参考频率的方法。该方法能有效结合二者优势，缩短频率的稳定时间，降低输出杂散。通过FPGA的控制、配置，产生了最佳性能的LS波段宽带步进频率信号，具有功耗低、集成度高、输出频率杂散抑制良好等特点。

Design of Wideband Step Frequency Signal Source Based on FPGA

Design and implementation of broadband stepped frequency signal source based on FPGA and phase-locked frequency synthe-sizer chip ADF4350 are introduced in this paper. By analyzing the two different implementation methods, the design determines a way of using scanning frequency of the DDS output to control the phase-locked loop phase reference frequency. The program can effectively combine advantages of both methods, it can shorten the frequency stabilization time and reduce the output spurious . Through the FPGA control and configuration, it produces the best performance of the LS-band stepped frequency signal, featuring low power, high integra-tion and output frequency with good stray spurious suppression.