FPGA的数字脉冲延时发生器设计

本文主要介绍了一种数字式脉冲延时发生器的设计方法,该方案是基于Altera(被Intel收购)的Cyclone Ⅳ系列FPGA实现的,为了同时满足高延时分辨率与大的可调范围,采用了粗细结合的延时方法,粗延时通过计数器法实现,细延时通过AD9501专用延时芯片实现;为了让用户与系统进行通信,在FPGA内部构建了Nios Ⅱ软核处理器,并且编写软件程序实现人机交互。对系统的关键模块进行了仿真,仿真结果显示模块设计符合需求,最终延时系统可以实现精度为16.5 ps、可调范围约为1.1 s的延时。

Design of Digital Pulse Delay Generator Based on FPGA

In the paper,a design method of digital pulse delay generator is designed,which is based on Altera's cyclone Ⅳ series FPGA.In order to meet the requirements of high delay resolution and large adjustable range,combine the coarse delay and fine delay,the coarse delay is realized by counter method,and the fine delay is realized by AD9501 special delay chip.In order to enable users to communicate with the system,Nios Ⅱ softcore processor is built in FPGA,and software program is written to realize human-computer interaction.The key modules of the system are simulated,and the simulation results show that the module design meets the requirements.The final delay system can achieve a delay accuracy of 16.5 ps and a dynamic range of 1.1 s.