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A new intelligent hardware implementation based on field programmable gate array for chaotic systems
Affiliation:1. Department of Mechanical Engineering, Universiti Teknologi Petronas, Malaysia;2. Department Civil Engineering, Universiti Teknologi Petronas, Malaysia;1. Department of Computer Science, Pondicherry University, Pondicherry, India;2. Department of ECE/MIT, Pondicherry, India;3. Department of Computer Science, RGET, Pondicherry, India;1. School of Electrical & Automatic Engineering, Changshu Institute of Technology, 215500 Changshu, China;2. School of Automation, Nanjing University of Science & Technology, 210094 Nanjing, China;1. Department of Information Systems Management and GREC Group, Esade – Universitat Ramon Llull, Barcelona, Spain;2. Department of Neonatology, Máxima Medical Center, The Netherlands;3. Department of Applied Mathematics 2 and GREC Group, Technical University of Catalonia, UPC-BarcelonaTech, Barcelona, Spain;1. Pondicherry University (A Central University of India), India;2. Periyar Govt. College, Cuddalore, India;3. National University of Kaohsiung, Taiwan
Abstract:
Keywords:Intelligent hardware implementation  The intelligent system model  MVPDOC  FPGA
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