IEC60044-8标准中CRC校验码的硬件实现

为确保电力通信系统数据的可靠传输，需要在数据链路中加入差错检测码。依据电子式电流互感器标准IEC60044-8的链路层规则，针对帧格式的CRC循环冗余校验码，在串行实现的基础上设计了8位并行CRC逻辑电路，并在FPGA上得到实现。与串行CRC相比，并行的编码速度大为提高。这种编码具有很高的实时性，满足了IEC60044-8标准所规定的快速性要求，达到了预定的目标，可方便地应用于电力通信系统，具有广泛的推广应用价值。

Hardware Implementation of CRC Code in IEC60044-8 Standard

In order to ensure reliable data transmission in electric power system, it is necessary to add error detection cede into data link. In accordance with link layer rules in the IEC60044-8 standard and the frame format of cyclic redundancy check cede, on the basis of serial implementation, the 8-bit parallel CRC logical circuit is designed and has been implemented in FPGA. Comparing with serial CRC, the speed of parallel encoding is faster. The parallel encoding features high performance of real time and meets the requirement of high speed stated in IEC60044-8 standard , reaches the anticipated target, can be conveniently applied to communication system in electric power enterprises. It is worth to be widely propagated and applied.