| 基于FPGA的虚拟逻辑分析仪的设计与实现 |
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| 引用本文： | 王万昭,张鹏云,和志强.基于FPGA的虚拟逻辑分析仪的设计与实现[J].计算机与现代化,2014,0(1):211-213,218. |
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| 作者姓名： | 王万昭 张鹏云 和志强 |
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| 作者单位： | [1]河北经贸大学信息技术学院,河北石家庄050061 [2]河北经贸大学科研处,河北石家庄050061 |
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| 基金项目： | 基金项目：河北省科技支撑项目（13210310D） |
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| 摘 要： | 介绍一种基于FPGA芯片的虚拟逻辑分析仪,它由信号调整电路、采样模块、触发模块、通信模块、数据处理模块(NIOS II软核)以及总线接口等组成,实现了8路并行采样,其采样速率可以达到100MS/s。
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| 关 键 词： | 并行采样 NIOS 调整电路 采样模块 触发模块 通信模块 |
Design and Implementation of Virtual Logic Analyzer Based on FPGA |
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| WANG Wan-zhao,ZHANG Peng-yun,HE Zhi-qiang.Design and Implementation of Virtual Logic Analyzer Based on FPGA[J].Computer and Modernization,2014,0(1):211-213,218. |
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| Authors: | WANG Wan-zhao ZHANG Peng-yun HE Zhi-qiang |
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| Affiliation: | 1. College of Information Technology, Hebei University of Economics and Business, Shijiazhuang 050061, China; 2. Research Dept., Hebei University of Economics and Business, Shijiazhuang 050061, China) |
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| Abstract: | This paper introduces a virtual logic analyzer based on FPGA chip, which consists of signal conditioning circuit, sam- pling module, trigger module, communication module, NIOS II soft-core, and bus interface. The 8-way parallel sampling is a- chieved. The sampling rate is up to 100MS/s. |
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| Keywords: | parallel sampling NIOS signal conditioning circuit sampling module trigger module communication module |
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