Architecture for video coding on a processor with an ARM and DSP cores |
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Authors: | Yung-Sung Huang Bin-Chang Chieu |
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Affiliation: | (1) National Taiwan University of Science and Technology, Taipei, Taiwan, Republic of China |
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Abstract: | This paper aims to describe architecture for video coding on a processor with an ARM and DSP cores. The proposed platform
has been designed for MPEG-4 Visual Simple Profile. The obtained results are optimized if compared with these of single-core.
The dual-core processors, composed of RISC and DSP, are widely used as the based-band processors of cell phones. The RISC
suits for IO control, while DSP is useful for computation. The operational efficiency of the integration of RISC and DSP is
outstanding. Video compression requires a great deal of computation, so we take both the feature of coding algorithm and the
hardware platform into consideration. We analyze features of key components in video codec and propose the framework, which
adopts DMA to shorten the time needed. It is the result of the communication between the dual-cores. The experimental results
indicate that during the inter-frame processing, dual-core with DMA can cut down the processing time by 1/4 more than that
of single-use of ARM or DSP. Moreover, it can save 3/4 of the time for encode/decode processing in inter-frame. Especially,
in respect of motion estimation, the performance rating can be improved by 4 times. |
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