The exception handler of multithreaded processors

Threading is one of the effective schemes to improve the performance of processors. This paper uses the threading scheme to implement a multithreaded processor, which is the combination of several thread slots （also called thread processing unit） and Thread Communication Unit （TCU）. The thread slots are accomplished by the pipeline processors that are constructed by General-Purpose-Registers （GPR）, function units, write-back unit, program counter, and control unit. TCU includes the thread dispatcher for managing the thread parallelism and instruction parallelism, and the communication unit can control and transmit the dependency data and interrupt signal when data dependency occurs among thread slots. The contribution of this proposed multiprocessor system is a central exception handler （CEHer） to be embedded to handle and manage the interrupt-request of thread slots. The interrupt signal is issued from control unit when data are missed in the local general purpose register, then to assert the CEHer to reduce access latency time of the needed data while the switching-context is among threads. To verify this proposed architecture, this proposed multithreaded processor is simulated in the model-level using petri net graph, and this proposed architecture is simulated using the SimpleScalar 2.0 simulation tools to analyze its performance. The simulation results show that this proposed architecture has better performance, such as data access latency, synchronous hide affection, communication latency, and CPI than that of the multiprocessor systems which use the distributed controller structure.

The exception handler of multithreaded processors