一种高效结构的多输入浮点加法器在FPGA上的实现

传统的多输入浮点加法运算是通过级联二输入浮点加法器来实现的，这种结构不可避免地使运算时延和所需逻辑资源成倍增加，从而越来越难以满足需要进行高速数字信号处理的需求。本文提出了一种适合在FPGA上实现的浮点数据格式和可以在四级流水线内完成的一种高效多输入浮点加法器结构，并给出了在Xilinx公司Virtex系列芯片上的测试
试数据。

Implementation of a Structure-Efficient Multiple-Input Floating-Point Adder on FPGAs

A multiple-input floating-point adder is usually composed of several double-input floating-point adders,and it is inevitable to increase the logic resources and processing latency,which makes it harder and harder to meet the requirements of high-speed digital signal processing.This article puts forward a new floating-point format suitable for implementation on FPGAs and an efficient structure with which the adder can complete calculating within four clock cycles.Test data is presented at the end of this article.