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多核处理器Cache一致性协议关键技术研究
引用本文:黄安文,张民选.多核处理器Cache一致性协议关键技术研究[J].计算机工程与科学,2009,31(Z1).
作者姓名:黄安文  张民选
作者单位:国防科技大学计算机学院并行与分布处理国防科技重点实验室,湖南,长沙,410073
基金项目:国家863计划基金资助项目,教育部"高性能微处理器设计创新团队"资助项目 
摘    要:多核处理器规模的不断扩大和核间通信机制的日益复杂,使得Cache一致性维护变得更加困难。本文从多核处理器Cache一致性问题的产生背景出发,分析监听协议、目录协议、Token协议和Hammer协议的实现机制以及在多核环境中的优缺点,分别从一致性协议与片上互连结构协同设计、面向低功耗应用的协议优化策略、Cache一致性协议验证及容错机制等角度考虑,对未来多核处理器Cache一致性协议设计的发展趋势和技术挑战进行详细分析与讨论。

关 键 词:Cache一致性  片上互连  低功耗  验证  容错

Key Techniques of Cache Coherence Protocol for Multi-Core Processor
HUANG An-wen,ZHANG Min-xuan.Key Techniques of Cache Coherence Protocol for Multi-Core Processor[J].Computer Engineering & Science,2009,31(Z1).
Authors:HUANG An-wen  ZHANG Min-xuan
Abstract:How to maintain the cache coherence becomes an intractable issue as the multi-core scales and communication mechanism between cores is complicated. After introducing the background of cache coherence in multi-core processor, this paper analyses the principles of traditional cache coherence protocols based on snooping, directory, Token and Hammer, respectively. The advantages and disadvantages are discussed in detail. Finally, the development trends and potential challenges are explored from the perspective of co-design of coherence protocol and on-chip interconnection, power-aware cache coherence policy, verification of coherence protocol, and fault-tolerant coherence protocol, respectively.
Keywords:cache coherence  on-chip interconnect  low power consumption  verification  fault tolerant
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