一种快速SIMD浮点乘加器的设计与实现

本文设计和实现了5级全流水SIMD浮点乘加器,支持双精度和双单精度浮点乘法、乘累加(减)操作,用Modelsim和NC Verilog测试和验证了RTL代码实现,基于65nm工艺采用Synopsys公司的Design Complier工具综合硬件实现,运行频率可达714.286MHz。结果表明,相比文献[3]中经典的低延迟乘加结构,在相同综合条件下性能提升了17.89%,面积增加了6.61%,功耗降低了25.08%。

Design and Implementation of a Fast SIMD Floating-Point Fused Multiply-Add Unit

A new 5-stage pipelined architecture of floating-point fused multiply-add (FMAC) unit is proposed and implemented. In this architecture, double precision or double-single precision floating-point multiply,multiply-add and multiply-subtract operations are supported. The unit is implemented to RTL Code, and simulated and verified in Modelsim and NC Verilog. Further more, it is synthesized in the 65nm CMOS technology by Design Complier of Synopsys, and the frequency reaches 714.286MHz.In addition, compared with the conventional low-delay FMAC of paper [3] in the same environment, apart from 6.61 percent of area which could be acceptable is increased, 17.89 percent of delay and 25.08 percent of power is reduced.