通过两个取指令部件消除流水线控制相关延迟

分支预测技术能够在一定程序上消除指令间的控制相关延迟，提高微处理器的性能，是微处理器设计的一项关键技术，一般说来，静态分支预测效率低，动态分支预测硬件复杂度高，嵌入式微处理器具有功耗低、硬件复杂度低等特点，这决定了它必须采用特殊的分支处理技术，本文提出了一种面向嵌入式微处理器的分支处理技术，利用双端口指 指令Cache,加上预期指令，在编译器的共同配合下，消除由控制相关引起的延迟，模拟结果表明，该技术具有硬件复杂度低，实现简单、控制相关消除率高等优点。

Reducing Pipeline Delay Using Two Instruction Fetching Units

Branch prediction can reduce the latency of control dependence between instructions to some extent, which is a key technique in microprocessor design in order to increase the performance of microprocessors. Generally speaking,static branching predicts in a low-efficiency way, while dynamic branch prediction needs complex hardware . Embeded microprocessors features low dissipation and low hardware complexity. This decides it must adopt special branching technigues. This paper presents an embeded-microprocessor-oriented branching technique, which uses double-port caches and prefetch instructions to reduce the latency caused by control dependence with the help of the compiler. Experimental results show that the technique features low hardware complexity, simple implementation and high reduction rate of control dependence.