小面积高性能的SHA-1/SHA-256/SM3IP复用电路的设计

Hash算法的快速发展导致了两个问题,一个是旧算法与新算法在应用于产品时更新换代的问题,另一个是基于应用环境的安全性选择不同算法时的复用问题。为解决这两个问题,实现了SHA-1/SHA-256/SM3算法的IP复用电路,电路采用循环展开方式,并加入流水线的设计,在支持多种算法的同时,还具有小面积高性能的优势。首先,基于Xilinx Virtex-6FPGA对电路设计进行性能分析,电路共占用776Slice单元,最大吞吐率可以达到0.964Gbps。然后,采用SMIC 0.13μm CMOS工艺实现了该设计,最后电路的面积是30.6k门,比单独实现三种算法的电路面积总和减小了41.7%,工作频率是177.62 MHz,最大吞吐率达到1.34Gbps。

An SHA-1/SHA-256/SM3 IP multiplexing circuit with small area and high performance

Abstract:The rapid development of Hash algorithm leads to two problems: one is the replacement of the old algorithms with the new ones when the products are upgraded, and the other is how to choose from different algorithms according to the security of the application environments. To solve the problems mentioned above, we design an SHA-1/SHA-256/SM3 IP multiplexing circuit, which makes use of the loop unfolding technique and adds pipelines to each circuit. The circuit not only supports a variety of hash algorithms, but also features small area and high performance. The design is first implemented on a Xilinx Virtex-6 FPGA. It requires 776 slices and achieves a maximum throughput of 0.964Gbps. Then we also implement every circuit using the SMIC 0.13μm CMOS technology. The area of the circuit is 30.6k gates, which is reduced by 41.7% than that of the three circuits combined. Besides, the operating frequency of the circuit is 177.62 MHz, and the maximum throughput reaches 1.34Gbps.