调整门和连线尺寸以减小串扰的拉格朗日松弛法

本文给出了一个布线后减小串扰噪声的算法。该算法通过调整逻辑门和互连线的尺寸有效地减小了串扰噪声，在减小噪声的同时约束电路的最大延时，使得在串扰噪声和时序都满足约束的条件下最小化芯片面积。算法保证了改变逻辑门和线网尺寸不会破坏电路的时序约束。实验结果证明，本算法有效地减小了串扰。此算法不需回到布线阶段来优
优化串扰，减少了设计迭代次数，加快了设计收敛时间。

Gate and Wire Sizing for Crosstalk Reduction by Lagrangian Relaxation

This paper presents a post-route crosstalk reduction algorithm by gate and wire sizing.At the same time,it constrains the worst delay of circuits to guarantee the circuit performance.This algorithm can minimize the total area of circuits subject to the worst delay and the maximum crosstalk bound,and then it does not lead to timing violation when performing gate and wire sizing.Experimental results demonstrate the effectiveness of the algorithm.What is more,it need not come back to the routing phase to reduce crosstalk,so it reduces the design iteration number and accelerates the convergence of design.