优化的JPEG2000算术编码器结构

各种并行位平面编码算法极大提高了上下文/符号数据对的产生速度,与此同时,算术编码算法的串行本质却严重限制了这些数据对的编码速度。因此,算术编码器(AE)已经成为JPEG2000系统的瓶颈问题。本文分析了现存各种算术编码器结构的缺陷,并提出了一种优化的单输入三级流水线结构。FPGA实现结果表明,本文结构以最小的硬件代价(1100 ALUTs和365 registers)获得了最优的实际数据吞吐率((133N)/(N+2))。

An Optimized Archeitecture for the Arithemetic Encoder of JPEG2000

Many parallel schemes for bit-plane coding of JPEG2000 have been proposed to speed up the generation of the CX/D pairs, while the serial inherence of arithmetic coding limits the speed of coding these pairs greatly. Therefore the a-rithmetic encoder (AE) is the actual bottleneck of the JPEG2000 system. In this paper, an optimized single-symbol 3-stage pipeline architecture for AE is presented, which makes up the flaws of the existing ones. Results from the FPGA-based im-plementations show that our proposal has the best actual throughput ((133N)/(N + 2)) with the least hardware resources (1100 ALUTs and 365 registers).