DDR4并行互连传输串扰特性仿真与分析

为满足高带宽存储应用需求，访存速率和互连密度越来越高。DDR4作为主存领域应用广泛且速率较快的并行存储互连技术，上升/下降沿时间或低至百ps量级，信号间串扰不容忽视。以某DDR4驱动模型和板级嵌入式应用为研究对象，建立多线打扰模型，从时域角度仿真分析布线间距、打扰源相位、数据速率、耦合传输线长对带状线传输串扰的影响。结果显示：5倍介质厚度布线间距条件下串扰接近于0 mV，不同相位关系打扰源形成的总串扰具有成倍双向差异。对于特定访存速率，耦合传输线长度与串扰极值存在周期性对应关系，据此合理设计DDR数据组线长，可以有效规避串扰极大值。

Crosstalk simulation and analysis of DDR4 parallel interconnection

Due to ever increasing demand for memory bandwidth, memory access rate and interconnect density become higher and higher. DDR4, as a very popular and fast parallel interconnect technology in main memory, features 100ps level of signal rise/fall time, which brings noticeable crosstalk issue between signals. Thus we design a trilinear disturbance model based on a certain DDR driver model and its board-level embedded application, and respectively simulate the effect of four factors on striline transmission crosstalk from the time domain angle, including line space, disturbing source phase, date rate, and coupling transmission line length. The results show that the crosstalk is close to 0 mV when the line pace reaches 5 times of dielectric thickness and different disturbing source phases cause double two-dimensional difference in total crosstalk. For a certain data rate, a periodic relationship between coupling transmission line length and extreme value of crosstalk is revealed. Utilizing this relationship to design reasonable line length for DDR data groups, crosstalk maximum value is avoidable. Key words: